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Alif Semiconductor /AE302F40C1537LE_CM55_HP_View /DSI /DSI_PHY_ULPS_CTRL

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Interpret as DSI_PHY_ULPS_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PHY_TXREQULPSCLK)PHY_TXREQULPSCLK 0 (PHY_TXEXITULPSCLK)PHY_TXEXITULPSCLK 0 (PHY_TXREQULPSLAN)PHY_TXREQULPSLAN 0 (PHY_TXEXITULPSLAN)PHY_TXEXITULPSLAN

Description

PHY ULPS Control Register

Fields

PHY_TXREQULPSCLK

ULPS mode Request on clock lane.
PHY_TXEXITULPSCLK

ULPS mode Exit on clock lane.
PHY_TXREQULPSLAN

ULPS mode Request on all active data lanes.
PHY_TXEXITULPSLAN

ULPS mode Exit on all active data lanes.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data